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Editorial

Peggy Aycinena
EDA Weekly
The Best of Times, The Worst of Time: Part 2 Since Part 1 of this article was published on October 13th, events have begun to overwhelm. The dramatic speed with which the …

Mark Gilbert
Careers Corner
Remember that kids' nursery rhyme LAYOFFS, FREEZES, GENERAL DOWNTURN… O MY?

Dr. Russ Henke & Dr. Jack Horgan
EDA & IP Commentary
Commentary: Electronics IP Industry - A November 2008 Update

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Jobs

Architectural Peformance Software Architect for Sun Microsystems at Santa Clara, CA

Senior R&D Engineer for Real Intent, Inc. at Sunnyvale, CA

Software Technical Lead for Sun Microsystems at Santa Clara, CA

Technical Marketing Engineer (CMT) for Mentor Graphics Corporation at Katowice, Poland

Senior PLACE AND ROUTE ENGINEER R&D for EDA Careers at San Jose, CA

Chip Integration Lead for Sun Microsystems at Santa Clara, CA

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Books For Sale

Complete PCB Design Using OrCad Capture and Layout, by Kraig Mitzner.

Fundamentals of Electric Circuits with CD-ROM, by Charles Alexander, Matthew Sadiku.

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Upcoming Events

DASIP 2008 at Université Libre de Bruxelles Belgium - Nov 24 - 26, 2008

SPS/IPC/DRIVES 2008 at Karl-Schönleben-Strasse Nuremberg Germany - Nov 25 - 27, 2008

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Tutorials

Verilogger Pro Animated Tutorial

Taking the Mystery out of the Infamous Formula, "SNR=6.02N + 1.76dB," and Why You Should Care

ADC Architectures III: Sigma-Delta ADC Basics

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